/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/**********************************************************************************************************************
 * File Name    : mipi_dsi__iobitmask.h
 * Version      : 1.00
 * Description  : IO bit mask file for mipi_dsi.
 *********************************************************************************************************************/

#ifndef MIPI_DSI_IOBITMASK_H
#define MIPI_DSI_IOBITMASK_H

#define R_MIPI_DSI_DSIDPHYCTRL0_EN_BGR_Msk                (0x00000001UL)
#define R_MIPI_DSI_DSIDPHYCTRL0_EN_BGR_Pos                (0UL)
#define R_MIPI_DSI_DSIDPHYCTRL0_EN_LDO1200_Msk            (0x00000002UL)
#define R_MIPI_DSI_DSIDPHYCTRL0_EN_LDO1200_Pos            (1UL)
#define R_MIPI_DSI_DSIDPHYCTRL0_RE_VDD_DETVCCQLV18_Msk    (0x00000004UL)
#define R_MIPI_DSI_DSIDPHYCTRL0_RE_VDD_DETVCCQLV18_Pos    (2UL)
#define R_MIPI_DSI_DSIDPHYCTRL0_CMN_MASTER_EN_Msk         (0x00000100UL)
#define R_MIPI_DSI_DSIDPHYCTRL0_CMN_MASTER_EN_Pos         (8UL)
#define R_MIPI_DSI_DSIDPHYCTRL0_CAL_EN_HSRX_OFS_Msk       (0x00010000UL)
#define R_MIPI_DSI_DSIDPHYCTRL0_CAL_EN_HSRX_OFS_Pos       (16UL)
#define R_MIPI_DSI_DSIDPHYTIM0_T_INIT_Msk                 (0x0007FFFFUL)
#define R_MIPI_DSI_DSIDPHYTIM0_T_INIT_Pos                 (0UL)
#define R_MIPI_DSI_DSIDPHYTIM0_TCLK_MISS_Msk              (0xFF000000UL)
#define R_MIPI_DSI_DSIDPHYTIM0_TCLK_MISS_Pos              (24UL)
#define R_MIPI_DSI_DSIDPHYTIM1_TCLK_SETTLE_Msk            (0x000000FFUL)
#define R_MIPI_DSI_DSIDPHYTIM1_TCLK_SETTLE_Pos            (0UL)
#define R_MIPI_DSI_DSIDPHYTIM1_THS_SETTLE_Msk             (0x0000FF00UL)
#define R_MIPI_DSI_DSIDPHYTIM1_THS_SETTLE_Pos             (8UL)
#define R_MIPI_DSI_DSIDPHYTIM1_TCLK_PREPARE_Msk           (0x00FF0000UL)
#define R_MIPI_DSI_DSIDPHYTIM1_TCLK_PREPARE_Pos           (16UL)
#define R_MIPI_DSI_DSIDPHYTIM1_THS_PREPARE_Msk            (0xFF000000UL)
#define R_MIPI_DSI_DSIDPHYTIM1_THS_PREPARE_Pos            (24UL)
#define R_MIPI_DSI_DSIDPHYTIM2_TCLK_ZERO_Msk              (0x000000FFUL)
#define R_MIPI_DSI_DSIDPHYTIM2_TCLK_ZERO_Pos              (0UL)
#define R_MIPI_DSI_DSIDPHYTIM2_TCLK_PRE_Msk               (0x0000FF00UL)
#define R_MIPI_DSI_DSIDPHYTIM2_TCLK_PRE_Pos               (8UL)
#define R_MIPI_DSI_DSIDPHYTIM2_TCLK_POST_Msk              (0x00FF0000UL)
#define R_MIPI_DSI_DSIDPHYTIM2_TCLK_POST_Pos              (16UL)
#define R_MIPI_DSI_DSIDPHYTIM2_TCLK_TRAIL_Msk             (0xFF000000UL)
#define R_MIPI_DSI_DSIDPHYTIM2_TCLK_TRAIL_Pos             (24UL)
#define R_MIPI_DSI_DSIDPHYTIM3_THS_ZERO_Msk               (0x000000FFUL)
#define R_MIPI_DSI_DSIDPHYTIM3_THS_ZERO_Pos               (0UL)
#define R_MIPI_DSI_DSIDPHYTIM3_THS_TRAIL_Msk              (0x0000FF00UL)
#define R_MIPI_DSI_DSIDPHYTIM3_THS_TRAIL_Pos              (8UL)
#define R_MIPI_DSI_DSIDPHYTIM3_THS_EXIT_Msk               (0x00FF0000UL)
#define R_MIPI_DSI_DSIDPHYTIM3_THS_EXIT_Pos               (16UL)
#define R_MIPI_DSI_DSIDPHYTIM3_TLPX_Msk                   (0xFF000000UL)
#define R_MIPI_DSI_DSIDPHYTIM3_TLPX_Pos                   (24UL)
#define R_MIPI_DSI_ISR_SQ0_Msk                            (0x00000001UL)
#define R_MIPI_DSI_ISR_SQ0_Pos                            (0UL)
#define R_MIPI_DSI_ISR_SQ1_Msk                            (0x00000010UL)
#define R_MIPI_DSI_ISR_SQ1_Pos                            (4UL)
#define R_MIPI_DSI_ISR_VIN1_Msk                           (0x00000100UL)
#define R_MIPI_DSI_ISR_VIN1_Pos                           (8UL)
#define R_MIPI_DSI_ISR_RCV_Msk                            (0x00001000UL)
#define R_MIPI_DSI_ISR_RCV_Pos                            (12UL)
#define R_MIPI_DSI_ISR_FERR_Msk                           (0x00010000UL)
#define R_MIPI_DSI_ISR_FERR_Pos                           (16UL)
#define R_MIPI_DSI_ISR_PPI_Msk                            (0x00100000UL)
#define R_MIPI_DSI_ISR_PPI_Pos                            (20UL)
#define R_MIPI_DSI_LINKSR_SQCHRUN0_Msk                    (0x00000001UL)
#define R_MIPI_DSI_LINKSR_SQCHRUN0_Pos                    (0UL)
#define R_MIPI_DSI_LINKSR_SQCHRUN1_Msk                    (0x00000010UL)
#define R_MIPI_DSI_LINKSR_SQCHRUN1_Pos                    (4UL)
#define R_MIPI_DSI_LINKSR_VICHRUN1_Msk                    (0x00000100UL)
#define R_MIPI_DSI_LINKSR_VICHRUN1_Pos                    (8UL)
#define R_MIPI_DSI_LINKSR_HSBUSY_Msk                      (0x00001000UL)
#define R_MIPI_DSI_LINKSR_HSBUSY_Pos                      (12UL)
#define R_MIPI_DSI_LINKSR_LPBUSY_Msk                      (0x00002000UL)
#define R_MIPI_DSI_LINKSR_LPBUSY_Pos                      (13UL)
#define R_MIPI_DSI_TXSETR_NUMLANE_Msk                     (0x00000003UL)
#define R_MIPI_DSI_TXSETR_NUMLANE_Pos                     (0UL)
#define R_MIPI_DSI_TXSETR_CLEN_Msk                        (0x00000100UL)
#define R_MIPI_DSI_TXSETR_CLEN_Pos                        (8UL)
#define R_MIPI_DSI_TXSETR_DLEN_Msk                        (0x00000200UL)
#define R_MIPI_DSI_TXSETR_DLEN_Pos                        (9UL)
#define R_MIPI_DSI_TXSETR_NUMLANECAP_Msk                  (0x00030000UL)
#define R_MIPI_DSI_TXSETR_NUMLANECAP_Pos                  (16UL)
#define R_MIPI_DSI_HSCLKSETR_HSCLKRUN_Msk                 (0x00000001UL)
#define R_MIPI_DSI_HSCLKSETR_HSCLKRUN_Pos                 (0UL)
#define R_MIPI_DSI_HSCLKSETR_HSCLKMODE_Msk                (0x00000002UL)
#define R_MIPI_DSI_HSCLKSETR_HSCLKMODE_Pos                (1UL)
#define R_MIPI_DSI_ULPSSETR_ULPSWKUP_Msk                  (0x000000FFUL)
#define R_MIPI_DSI_ULPSSETR_ULPSWKUP_Pos                  (0UL)
#define R_MIPI_DSI_ULPSCR_CLULPSENT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_ULPSCR_CLULPSENT_Pos                   (24UL)
#define R_MIPI_DSI_ULPSCR_CLULPSEXT_Msk                   (0x02000000UL)
#define R_MIPI_DSI_ULPSCR_CLULPSEXT_Pos                   (25UL)
#define R_MIPI_DSI_ULPSCR_DLULPSENT_Msk                   (0x10000000UL)
#define R_MIPI_DSI_ULPSCR_DLULPSENT_Pos                   (28UL)
#define R_MIPI_DSI_ULPSCR_DLULPSEXT_Msk                   (0x20000000UL)
#define R_MIPI_DSI_ULPSCR_DLULPSEXT_Pos                   (29UL)
#define R_MIPI_DSI_RSTCR_SWRST_Msk                        (0x00000001UL)
#define R_MIPI_DSI_RSTCR_SWRST_Pos                        (0UL)
#define R_MIPI_DSI_RSTCR_FCETXSTP_Msk                     (0x00010000UL)
#define R_MIPI_DSI_RSTCR_FCETXSTP_Pos                     (16UL)
#define R_MIPI_DSI_RSTSR_SWRSTHS_Msk                      (0x00000001UL)
#define R_MIPI_DSI_RSTSR_SWRSTHS_Pos                      (0UL)
#define R_MIPI_DSI_RSTSR_SWRSTLP_Msk                      (0x00000002UL)
#define R_MIPI_DSI_RSTSR_SWRSTLP_Pos                      (1UL)
#define R_MIPI_DSI_RSTSR_SWRSTAPB_Msk                     (0x00000004UL)
#define R_MIPI_DSI_RSTSR_SWRSTAPB_Pos                     (2UL)
#define R_MIPI_DSI_RSTSR_SWRSTIB_Msk                      (0x00000008UL)
#define R_MIPI_DSI_RSTSR_SWRSTIB_Pos                      (3UL)
#define R_MIPI_DSI_RSTSR_SWRSTV1_Msk                      (0x00000010UL)
#define R_MIPI_DSI_RSTSR_SWRSTV1_Pos                      (4UL)
#define R_MIPI_DSI_RSTSR_DLSTPST_Msk                      (0x00000F00UL)
#define R_MIPI_DSI_RSTSR_DLSTPST_Pos                      (8UL)
#define R_MIPI_DSI_RSTSR_DL0DIR_Msk                       (0x00008000UL)
#define R_MIPI_DSI_RSTSR_DL0DIR_Pos                       (15UL)
#define R_MIPI_DSI_DSISETR_MRPSZ_Msk                      (0x0000FFFFUL)
#define R_MIPI_DSI_DSISETR_MRPSZ_Pos                      (0UL)
#define R_MIPI_DSI_DSISETR_ECCEN_Msk                      (0x00010000UL)
#define R_MIPI_DSI_DSISETR_ECCEN_Pos                      (16UL)
#define R_MIPI_DSI_DSISETR_CRCEN_Msk                      (0x00F00000UL)
#define R_MIPI_DSI_DSISETR_CRCEN_Pos                      (20UL)
#define R_MIPI_DSI_DSISETR_SCREN_Msk                      (0x20000000UL)
#define R_MIPI_DSI_DSISETR_SCREN_Pos                      (29UL)
#define R_MIPI_DSI_DSISETR_TEIDIR_Msk                     (0x40000000UL)
#define R_MIPI_DSI_DSISETR_TEIDIR_Pos                     (30UL)
#define R_MIPI_DSI_DSISETR_EOTPEN_Msk                     (0x80000000UL)
#define R_MIPI_DSI_DSISETR_EOTPEN_Pos                     (31UL)
#define R_MIPI_DSI_RXBUFSZR_RXBUFSZ_Msk                   (0x00F00000UL)
#define R_MIPI_DSI_RXBUFSZR_RXBUFSZ_Pos                   (20UL)
#define R_MIPI_DSI_TXPPD0R_DATA_Msk                       (0xFFFFFFFFUL)
#define R_MIPI_DSI_TXPPD0R_DATA_Pos                       (0UL)
#define R_MIPI_DSI_TXPPD1R_DATA_Msk                       (0xFFFFFFFFUL)
#define R_MIPI_DSI_TXPPD1R_DATA_Pos                       (0UL)
#define R_MIPI_DSI_TXPPD2R_DATA_Msk                       (0xFFFFFFFFUL)
#define R_MIPI_DSI_TXPPD2R_DATA_Pos                       (0UL)
#define R_MIPI_DSI_TXPPD3R_DATA_Msk                       (0xFFFFFFFFUL)
#define R_MIPI_DSI_TXPPD3R_DATA_Pos                       (0UL)
#define R_MIPI_DSI_RXSR_BTAREQEND_Msk                     (0x00000001UL)
#define R_MIPI_DSI_RXSR_BTAREQEND_Pos                     (0UL)
#define R_MIPI_DSI_RXSR_LRXHTO_Msk                        (0x00000002UL)
#define R_MIPI_DSI_RXSR_LRXHTO_Pos                        (1UL)
#define R_MIPI_DSI_RXSR_TATO_Msk                          (0x00000004UL)
#define R_MIPI_DSI_RXSR_TATO_Pos                          (2UL)
#define R_MIPI_DSI_RXSR_RXRESP_Msk                        (0x00000100UL)
#define R_MIPI_DSI_RXSR_RXRESP_Pos                        (8UL)
#define R_MIPI_DSI_RXSR_RXEOTP_Msk                        (0x00000400UL)
#define R_MIPI_DSI_RXSR_RXEOTP_Pos                        (10UL)
#define R_MIPI_DSI_RXSR_RXUK5TRG_Msk                      (0x00000800UL)
#define R_MIPI_DSI_RXSR_RXUK5TRG_Pos                      (11UL)
#define R_MIPI_DSI_RXSR_RXRTRG_Msk                        (0x00001000UL)
#define R_MIPI_DSI_RXSR_RXRTRG_Pos                        (12UL)
#define R_MIPI_DSI_RXSR_RXTE_Msk                          (0x00002000UL)
#define R_MIPI_DSI_RXSR_RXTE_Pos                          (13UL)
#define R_MIPI_DSI_RXSR_RXACK_Msk                         (0x00004000UL)
#define R_MIPI_DSI_RXSR_RXACK_Pos                         (14UL)
#define R_MIPI_DSI_RXSR_EXTTEDET_Msk                      (0x00008000UL)
#define R_MIPI_DSI_RXSR_EXTTEDET_Pos                      (15UL)
#define R_MIPI_DSI_RXSR_MLFERR_Msk                        (0x00010000UL)
#define R_MIPI_DSI_RXSR_MLFERR_Pos                        (16UL)
#define R_MIPI_DSI_RXSR_ECCERR_Msk                        (0x00020000UL)
#define R_MIPI_DSI_RXSR_ECCERR_Pos                        (17UL)
#define R_MIPI_DSI_RXSR_UEXPKTERR_Msk                     (0x00040000UL)
#define R_MIPI_DSI_RXSR_UEXPKTERR_Pos                     (18UL)
#define R_MIPI_DSI_RXSR_WCERR_Msk                         (0x00100000UL)
#define R_MIPI_DSI_RXSR_WCERR_Pos                         (20UL)
#define R_MIPI_DSI_RXSR_CRCERR_Msk                        (0x00200000UL)
#define R_MIPI_DSI_RXSR_CRCERR_Pos                        (21UL)
#define R_MIPI_DSI_RXSR_IBERR_Msk                         (0x00400000UL)
#define R_MIPI_DSI_RXSR_IBERR_Pos                         (22UL)
#define R_MIPI_DSI_RXSR_RXOVFERR_Msk                      (0x00800000UL)
#define R_MIPI_DSI_RXSR_RXOVFERR_Pos                      (23UL)
#define R_MIPI_DSI_RXSR_PRESPTOERR_Msk                    (0x01000000UL)
#define R_MIPI_DSI_RXSR_PRESPTOERR_Pos                    (24UL)
#define R_MIPI_DSI_RXSR_NORETERR_Msk                      (0x02000000UL)
#define R_MIPI_DSI_RXSR_NORETERR_Pos                      (25UL)
#define R_MIPI_DSI_RXSR_MAXRPSZERR_Msk                    (0x04000000UL)
#define R_MIPI_DSI_RXSR_MAXRPSZERR_Pos                    (26UL)
#define R_MIPI_DSI_RXSR_ECCERR1B_Msk                      (0x10000000UL)
#define R_MIPI_DSI_RXSR_ECCERR1B_Pos                      (28UL)
#define R_MIPI_DSI_RXSR_RXAKE_Msk                         (0x40000000UL)
#define R_MIPI_DSI_RXSR_RXAKE_Pos                         (30UL)
#define R_MIPI_DSI_RXSCR_BTAREQEND_Msk                    (0x00000001UL)
#define R_MIPI_DSI_RXSCR_BTAREQEND_Pos                    (0UL)
#define R_MIPI_DSI_RXSCR_LRXHTO_Msk                       (0x00000002UL)
#define R_MIPI_DSI_RXSCR_LRXHTO_Pos                       (1UL)
#define R_MIPI_DSI_RXSCR_TATO_Msk                         (0x00000004UL)
#define R_MIPI_DSI_RXSCR_TATO_Pos                         (2UL)
#define R_MIPI_DSI_RXSCR_RXRESP_Msk                       (0x00000100UL)
#define R_MIPI_DSI_RXSCR_RXRESP_Pos                       (8UL)
#define R_MIPI_DSI_RXSCR_RXEOTP_Msk                       (0x00000400UL)
#define R_MIPI_DSI_RXSCR_RXEOTP_Pos                       (10UL)
#define R_MIPI_DSI_RXSCR_RXUK5TRG_Msk                     (0x00000800UL)
#define R_MIPI_DSI_RXSCR_RXUK5TRG_Pos                     (11UL)
#define R_MIPI_DSI_RXSCR_RXRTRG_Msk                       (0x00001000UL)
#define R_MIPI_DSI_RXSCR_RXRTRG_Pos                       (12UL)
#define R_MIPI_DSI_RXSCR_RXTE_Msk                         (0x00002000UL)
#define R_MIPI_DSI_RXSCR_RXTE_Pos                         (13UL)
#define R_MIPI_DSI_RXSCR_RXACK_Msk                        (0x00004000UL)
#define R_MIPI_DSI_RXSCR_RXACK_Pos                        (14UL)
#define R_MIPI_DSI_RXSCR_EXTTEDET_Msk                     (0x00008000UL)
#define R_MIPI_DSI_RXSCR_EXTTEDET_Pos                     (15UL)
#define R_MIPI_DSI_RXSCR_MLFERR_Msk                       (0x00010000UL)
#define R_MIPI_DSI_RXSCR_MLFERR_Pos                       (16UL)
#define R_MIPI_DSI_RXSCR_ECCERR_Msk                       (0x00020000UL)
#define R_MIPI_DSI_RXSCR_ECCERR_Pos                       (17UL)
#define R_MIPI_DSI_RXSCR_UEXPKTERR_Msk                    (0x00040000UL)
#define R_MIPI_DSI_RXSCR_UEXPKTERR_Pos                    (18UL)
#define R_MIPI_DSI_RXSCR_WCERR_Msk                        (0x00100000UL)
#define R_MIPI_DSI_RXSCR_WCERR_Pos                        (20UL)
#define R_MIPI_DSI_RXSCR_CRCERR_Msk                       (0x00200000UL)
#define R_MIPI_DSI_RXSCR_CRCERR_Pos                       (21UL)
#define R_MIPI_DSI_RXSCR_IBERR_Msk                        (0x00400000UL)
#define R_MIPI_DSI_RXSCR_IBERR_Pos                        (22UL)
#define R_MIPI_DSI_RXSCR_RXOVFERR_Msk                     (0x00800000UL)
#define R_MIPI_DSI_RXSCR_RXOVFERR_Pos                     (23UL)
#define R_MIPI_DSI_RXSCR_PRESPTOERR_Msk                   (0x01000000UL)
#define R_MIPI_DSI_RXSCR_PRESPTOERR_Pos                   (24UL)
#define R_MIPI_DSI_RXSCR_NORETERR_Msk                     (0x02000000UL)
#define R_MIPI_DSI_RXSCR_NORETERR_Pos                     (25UL)
#define R_MIPI_DSI_RXSCR_MAXRPSZERR_Msk                   (0x04000000UL)
#define R_MIPI_DSI_RXSCR_MAXRPSZERR_Pos                   (26UL)
#define R_MIPI_DSI_RXSCR_ECCERR1B_Msk                     (0x10000000UL)
#define R_MIPI_DSI_RXSCR_ECCERR1B_Pos                     (28UL)
#define R_MIPI_DSI_RXSCR_RXAKE_Msk                        (0x40000000UL)
#define R_MIPI_DSI_RXSCR_RXAKE_Pos                        (30UL)
#define R_MIPI_DSI_RXIER_BTAREQEND_Msk                    (0x00000001UL)
#define R_MIPI_DSI_RXIER_BTAREQEND_Pos                    (0UL)
#define R_MIPI_DSI_RXIER_LRXHTO_Msk                       (0x00000002UL)
#define R_MIPI_DSI_RXIER_LRXHTO_Pos                       (1UL)
#define R_MIPI_DSI_RXIER_TATO_Msk                         (0x00000004UL)
#define R_MIPI_DSI_RXIER_TATO_Pos                         (2UL)
#define R_MIPI_DSI_RXIER_RXRESP_Msk                       (0x00000100UL)
#define R_MIPI_DSI_RXIER_RXRESP_Pos                       (8UL)
#define R_MIPI_DSI_RXIER_RXEOTP_Msk                       (0x00000400UL)
#define R_MIPI_DSI_RXIER_RXEOTP_Pos                       (10UL)
#define R_MIPI_DSI_RXIER_RXUK5TRG_Msk                     (0x00000800UL)
#define R_MIPI_DSI_RXIER_RXUK5TRG_Pos                     (11UL)
#define R_MIPI_DSI_RXIER_RXRTRG_Msk                       (0x00001000UL)
#define R_MIPI_DSI_RXIER_RXRTRG_Pos                       (12UL)
#define R_MIPI_DSI_RXIER_RXTE_Msk                         (0x00002000UL)
#define R_MIPI_DSI_RXIER_RXTE_Pos                         (13UL)
#define R_MIPI_DSI_RXIER_RXACK_Msk                        (0x00004000UL)
#define R_MIPI_DSI_RXIER_RXACK_Pos                        (14UL)
#define R_MIPI_DSI_RXIER_EXTTEDET_Msk                     (0x00008000UL)
#define R_MIPI_DSI_RXIER_EXTTEDET_Pos                     (15UL)
#define R_MIPI_DSI_RXIER_MLFERR_Msk                       (0x00010000UL)
#define R_MIPI_DSI_RXIER_MLFERR_Pos                       (16UL)
#define R_MIPI_DSI_RXIER_ECCERR_Msk                       (0x00020000UL)
#define R_MIPI_DSI_RXIER_ECCERR_Pos                       (17UL)
#define R_MIPI_DSI_RXIER_UEXPKTERR_Msk                    (0x00040000UL)
#define R_MIPI_DSI_RXIER_UEXPKTERR_Pos                    (18UL)
#define R_MIPI_DSI_RXIER_WCERR_Msk                        (0x00100000UL)
#define R_MIPI_DSI_RXIER_WCERR_Pos                        (20UL)
#define R_MIPI_DSI_RXIER_CRCERR_Msk                       (0x00200000UL)
#define R_MIPI_DSI_RXIER_CRCERR_Pos                       (21UL)
#define R_MIPI_DSI_RXIER_IBERR_Msk                        (0x00400000UL)
#define R_MIPI_DSI_RXIER_IBERR_Pos                        (22UL)
#define R_MIPI_DSI_RXIER_RXOVFERR_Msk                     (0x00800000UL)
#define R_MIPI_DSI_RXIER_RXOVFERR_Pos                     (23UL)
#define R_MIPI_DSI_RXIER_PRESPTOERR_Msk                   (0x01000000UL)
#define R_MIPI_DSI_RXIER_PRESPTOERR_Pos                   (24UL)
#define R_MIPI_DSI_RXIER_NORETERR_Msk                     (0x02000000UL)
#define R_MIPI_DSI_RXIER_NORETERR_Pos                     (25UL)
#define R_MIPI_DSI_RXIER_MAXRPSZERR_Msk                   (0x04000000UL)
#define R_MIPI_DSI_RXIER_MAXRPSZERR_Pos                   (26UL)
#define R_MIPI_DSI_RXIER_ECCERR1B_Msk                     (0x10000000UL)
#define R_MIPI_DSI_RXIER_ECCERR1B_Pos                     (28UL)
#define R_MIPI_DSI_RXIER_RXAKE_Msk                        (0x40000000UL)
#define R_MIPI_DSI_RXIER_RXAKE_Pos                        (30UL)
#define R_MIPI_DSI_PRESPTOBTASETR_PRESPTOBTA_Msk          (0xFFFFFFFFUL)
#define R_MIPI_DSI_PRESPTOBTASETR_PRESPTOBTA_Pos          (0UL)
#define R_MIPI_DSI_PRESPTOLPSETR_PRESPTOLPW_Msk           (0x0000FFFFUL)
#define R_MIPI_DSI_PRESPTOLPSETR_PRESPTOLPW_Pos           (0UL)
#define R_MIPI_DSI_PRESPTOLPSETR_PRESPTOLPR_Msk           (0xFFFF0000UL)
#define R_MIPI_DSI_PRESPTOLPSETR_PRESPTOLPR_Pos           (16UL)
#define R_MIPI_DSI_PRESPTOHSSETR_PRESPTOHSW_Msk           (0x0000FFFFUL)
#define R_MIPI_DSI_PRESPTOHSSETR_PRESPTOHSW_Pos           (0UL)
#define R_MIPI_DSI_PRESPTOHSSETR_PRESPTOHSR_Msk           (0xFFFF0000UL)
#define R_MIPI_DSI_PRESPTOHSSETR_PRESPTOHSR_Pos           (16UL)
#define R_MIPI_DSI_AKEPLATIR_ERRRPTLAT_Msk                (0x0000FFFFUL)
#define R_MIPI_DSI_AKEPLATIR_ERRRPTLAT_Pos                (0UL)
#define R_MIPI_DSI_AKEPLATIR_VC0_Msk                      (0x00010000UL)
#define R_MIPI_DSI_AKEPLATIR_VC0_Pos                      (16UL)
#define R_MIPI_DSI_AKEPLATIR_VC1_Msk                      (0x00020000UL)
#define R_MIPI_DSI_AKEPLATIR_VC1_Pos                      (17UL)
#define R_MIPI_DSI_AKEPLATIR_VC2_Msk                      (0x00040000UL)
#define R_MIPI_DSI_AKEPLATIR_VC2_Pos                      (18UL)
#define R_MIPI_DSI_AKEPLATIR_VC3_Msk                      (0x00080000UL)
#define R_MIPI_DSI_AKEPLATIR_VC3_Pos                      (19UL)
#define R_MIPI_DSI_AKEPACMSR_ERRRPTACM_Msk                (0x0000FFFFUL)
#define R_MIPI_DSI_AKEPACMSR_ERRRPTACM_Pos                (0UL)
#define R_MIPI_DSI_AKEPACMSR_VC0_Msk                      (0x00010000UL)
#define R_MIPI_DSI_AKEPACMSR_VC0_Pos                      (16UL)
#define R_MIPI_DSI_AKEPACMSR_VC1_Msk                      (0x00020000UL)
#define R_MIPI_DSI_AKEPACMSR_VC1_Pos                      (17UL)
#define R_MIPI_DSI_AKEPACMSR_VC2_Msk                      (0x00040000UL)
#define R_MIPI_DSI_AKEPACMSR_VC2_Pos                      (18UL)
#define R_MIPI_DSI_AKEPACMSR_VC3_Msk                      (0x00080000UL)
#define R_MIPI_DSI_AKEPACMSR_VC3_Pos                      (19UL)
#define R_MIPI_DSI_AKEPSCR_ERRRPTACM_Msk                  (0x0000FFFFUL)
#define R_MIPI_DSI_AKEPSCR_ERRRPTACM_Pos                  (0UL)
#define R_MIPI_DSI_AKEPSCR_VC0_Msk                        (0x00010000UL)
#define R_MIPI_DSI_AKEPSCR_VC0_Pos                        (16UL)
#define R_MIPI_DSI_AKEPSCR_VC1_Msk                        (0x00020000UL)
#define R_MIPI_DSI_AKEPSCR_VC1_Pos                        (17UL)
#define R_MIPI_DSI_AKEPSCR_VC2_Msk                        (0x00040000UL)
#define R_MIPI_DSI_AKEPSCR_VC2_Pos                        (18UL)
#define R_MIPI_DSI_AKEPSCR_VC3_Msk                        (0x00080000UL)
#define R_MIPI_DSI_AKEPSCR_VC3_Pos                        (19UL)
#define R_MIPI_DSI_RXRSSR_SLT0VLD_Msk                     (0x00000001UL)
#define R_MIPI_DSI_RXRSSR_SLT0VLD_Pos                     (0UL)
#define R_MIPI_DSI_RXRSSR_SLT1VLD_Msk                     (0x00000002UL)
#define R_MIPI_DSI_RXRSSR_SLT1VLD_Pos                     (1UL)
#define R_MIPI_DSI_RXRSSR_SLT2VLD_Msk                     (0x00000004UL)
#define R_MIPI_DSI_RXRSSR_SLT2VLD_Pos                     (2UL)
#define R_MIPI_DSI_RXRSSR_SLT3VLD_Msk                     (0x00000008UL)
#define R_MIPI_DSI_RXRSSR_SLT3VLD_Pos                     (3UL)
#define R_MIPI_DSI_RXRSSCR_SLT0C_Msk                      (0x00000001UL)
#define R_MIPI_DSI_RXRSSCR_SLT0C_Pos                      (0UL)
#define R_MIPI_DSI_RXRSSCR_SLT1C_Msk                      (0x00000002UL)
#define R_MIPI_DSI_RXRSSCR_SLT1C_Pos                      (1UL)
#define R_MIPI_DSI_RXRSSCR_SLT2C_Msk                      (0x00000004UL)
#define R_MIPI_DSI_RXRSSCR_SLT2C_Pos                      (2UL)
#define R_MIPI_DSI_RXRSSCR_SLT3C_Msk                      (0x00000008UL)
#define R_MIPI_DSI_RXRSSCR_SLT3C_Pos                      (3UL)
#define R_MIPI_DSI_RXRINFOOWSR_SLT0INFOOW_Msk             (0x00000001UL)
#define R_MIPI_DSI_RXRINFOOWSR_SLT0INFOOW_Pos             (0UL)
#define R_MIPI_DSI_RXRINFOOWSR_SLT1INFOOW_Msk             (0x00000002UL)
#define R_MIPI_DSI_RXRINFOOWSR_SLT1INFOOW_Pos             (1UL)
#define R_MIPI_DSI_RXRINFOOWSR_SLT2INFOOW_Msk             (0x00000004UL)
#define R_MIPI_DSI_RXRINFOOWSR_SLT2INFOOW_Pos             (2UL)
#define R_MIPI_DSI_RXRINFOOWSR_SLT3INFOOW_Msk             (0x00000008UL)
#define R_MIPI_DSI_RXRINFOOWSR_SLT3INFOOW_Pos             (3UL)
#define R_MIPI_DSI_RXRINFOOWSCR_SLT0INFOOWC_Msk           (0x00000001UL)
#define R_MIPI_DSI_RXRINFOOWSCR_SLT0INFOOWC_Pos           (0UL)
#define R_MIPI_DSI_RXRINFOOWSCR_SLT1INFOOWC_Msk           (0x00000002UL)
#define R_MIPI_DSI_RXRINFOOWSCR_SLT1INFOOWC_Pos           (1UL)
#define R_MIPI_DSI_RXRINFOOWSCR_SLT2INFOOWC_Msk           (0x00000004UL)
#define R_MIPI_DSI_RXRINFOOWSCR_SLT2INFOOWC_Pos           (2UL)
#define R_MIPI_DSI_RXRINFOOWSCR_SLT3INFOOWC_Msk           (0x00000008UL)
#define R_MIPI_DSI_RXRINFOOWSCR_SLT3INFOOWC_Pos           (3UL)
#define R_MIPI_DSI_RXRSS0R_DATA0_Msk                      (0x000000FFUL)
#define R_MIPI_DSI_RXRSS0R_DATA0_Pos                      (0UL)
#define R_MIPI_DSI_RXRSS0R_DATA1_Msk                      (0x0000FF00UL)
#define R_MIPI_DSI_RXRSS0R_DATA1_Pos                      (8UL)
#define R_MIPI_DSI_RXRSS0R_DT_Msk                         (0x003F0000UL)
#define R_MIPI_DSI_RXRSS0R_DT_Pos                         (16UL)
#define R_MIPI_DSI_RXRSS0R_VC_Msk                         (0x00C00000UL)
#define R_MIPI_DSI_RXRSS0R_VC_Pos                         (22UL)
#define R_MIPI_DSI_RXRSS0R_FMT_Msk                        (0x01000000UL)
#define R_MIPI_DSI_RXRSS0R_FMT_Pos                        (24UL)
#define R_MIPI_DSI_RXRSS0R_RXSUC_Msk                      (0x02000000UL)
#define R_MIPI_DSI_RXRSS0R_RXSUC_Pos                      (25UL)
#define R_MIPI_DSI_RXRSS0R_RXFATALERR_Msk                 (0x04000000UL)
#define R_MIPI_DSI_RXRSS0R_RXFATALERR_Pos                 (26UL)
#define R_MIPI_DSI_RXRSS0R_RXFAIL_Msk                     (0x08000000UL)
#define R_MIPI_DSI_RXRSS0R_RXFAIL_Pos                     (27UL)
#define R_MIPI_DSI_RXRSS0R_RXPKTDFAIL_Msk                 (0x10000000UL)
#define R_MIPI_DSI_RXRSS0R_RXPKTDFAIL_Pos                 (28UL)
#define R_MIPI_DSI_RXRSS0R_RXCORERR_Msk                   (0x20000000UL)
#define R_MIPI_DSI_RXRSS0R_RXCORERR_Pos                   (29UL)
#define R_MIPI_DSI_RXRSS0R_RXAKE_Msk                      (0x40000000UL)
#define R_MIPI_DSI_RXRSS0R_RXAKE_Pos                      (30UL)
#define R_MIPI_DSI_RXRSS0R_INFOOW_Msk                     (0x80000000UL)
#define R_MIPI_DSI_RXRSS0R_INFOOW_Pos                     (31UL)
#define R_MIPI_DSI_RXRSS1R_DATA0_Msk                      (0x000000FFUL)
#define R_MIPI_DSI_RXRSS1R_DATA0_Pos                      (0UL)
#define R_MIPI_DSI_RXRSS1R_DATA1_Msk                      (0x0000FF00UL)
#define R_MIPI_DSI_RXRSS1R_DATA1_Pos                      (8UL)
#define R_MIPI_DSI_RXRSS1R_DT_Msk                         (0x003F0000UL)
#define R_MIPI_DSI_RXRSS1R_DT_Pos                         (16UL)
#define R_MIPI_DSI_RXRSS1R_VC_Msk                         (0x00C00000UL)
#define R_MIPI_DSI_RXRSS1R_VC_Pos                         (22UL)
#define R_MIPI_DSI_RXRSS1R_FMT_Msk                        (0x01000000UL)
#define R_MIPI_DSI_RXRSS1R_FMT_Pos                        (24UL)
#define R_MIPI_DSI_RXRSS1R_RXSUC_Msk                      (0x02000000UL)
#define R_MIPI_DSI_RXRSS1R_RXSUC_Pos                      (25UL)
#define R_MIPI_DSI_RXRSS1R_RXFATALERR_Msk                 (0x04000000UL)
#define R_MIPI_DSI_RXRSS1R_RXFATALERR_Pos                 (26UL)
#define R_MIPI_DSI_RXRSS1R_RXFAIL_Msk                     (0x08000000UL)
#define R_MIPI_DSI_RXRSS1R_RXFAIL_Pos                     (27UL)
#define R_MIPI_DSI_RXRSS1R_RXPKTDFAIL_Msk                 (0x10000000UL)
#define R_MIPI_DSI_RXRSS1R_RXPKTDFAIL_Pos                 (28UL)
#define R_MIPI_DSI_RXRSS1R_RXCORERR_Msk                   (0x20000000UL)
#define R_MIPI_DSI_RXRSS1R_RXCORERR_Pos                   (29UL)
#define R_MIPI_DSI_RXRSS1R_RXAKE_Msk                      (0x40000000UL)
#define R_MIPI_DSI_RXRSS1R_RXAKE_Pos                      (30UL)
#define R_MIPI_DSI_RXRSS1R_INFOOW_Msk                     (0x80000000UL)
#define R_MIPI_DSI_RXRSS1R_INFOOW_Pos                     (31UL)
#define R_MIPI_DSI_RXRSS2R_DATA0_Msk                      (0x000000FFUL)
#define R_MIPI_DSI_RXRSS2R_DATA0_Pos                      (0UL)
#define R_MIPI_DSI_RXRSS2R_DATA1_Msk                      (0x0000FF00UL)
#define R_MIPI_DSI_RXRSS2R_DATA1_Pos                      (8UL)
#define R_MIPI_DSI_RXRSS2R_DT_Msk                         (0x003F0000UL)
#define R_MIPI_DSI_RXRSS2R_DT_Pos                         (16UL)
#define R_MIPI_DSI_RXRSS2R_VC_Msk                         (0x00C00000UL)
#define R_MIPI_DSI_RXRSS2R_VC_Pos                         (22UL)
#define R_MIPI_DSI_RXRSS2R_FMT_Msk                        (0x01000000UL)
#define R_MIPI_DSI_RXRSS2R_FMT_Pos                        (24UL)
#define R_MIPI_DSI_RXRSS2R_RXSUC_Msk                      (0x02000000UL)
#define R_MIPI_DSI_RXRSS2R_RXSUC_Pos                      (25UL)
#define R_MIPI_DSI_RXRSS2R_RXFATALERR_Msk                 (0x04000000UL)
#define R_MIPI_DSI_RXRSS2R_RXFATALERR_Pos                 (26UL)
#define R_MIPI_DSI_RXRSS2R_RXFAIL_Msk                     (0x08000000UL)
#define R_MIPI_DSI_RXRSS2R_RXFAIL_Pos                     (27UL)
#define R_MIPI_DSI_RXRSS2R_RXPKTDFAIL_Msk                 (0x10000000UL)
#define R_MIPI_DSI_RXRSS2R_RXPKTDFAIL_Pos                 (28UL)
#define R_MIPI_DSI_RXRSS2R_RXCORERR_Msk                   (0x20000000UL)
#define R_MIPI_DSI_RXRSS2R_RXCORERR_Pos                   (29UL)
#define R_MIPI_DSI_RXRSS2R_RXAKE_Msk                      (0x40000000UL)
#define R_MIPI_DSI_RXRSS2R_RXAKE_Pos                      (30UL)
#define R_MIPI_DSI_RXRSS2R_INFOOW_Msk                     (0x80000000UL)
#define R_MIPI_DSI_RXRSS2R_INFOOW_Pos                     (31UL)
#define R_MIPI_DSI_RXRSS3R_DATA0_Msk                      (0x000000FFUL)
#define R_MIPI_DSI_RXRSS3R_DATA0_Pos                      (0UL)
#define R_MIPI_DSI_RXRSS3R_DATA1_Msk                      (0x0000FF00UL)
#define R_MIPI_DSI_RXRSS3R_DATA1_Pos                      (8UL)
#define R_MIPI_DSI_RXRSS3R_DT_Msk                         (0x003F0000UL)
#define R_MIPI_DSI_RXRSS3R_DT_Pos                         (16UL)
#define R_MIPI_DSI_RXRSS3R_VC_Msk                         (0x00C00000UL)
#define R_MIPI_DSI_RXRSS3R_VC_Pos                         (22UL)
#define R_MIPI_DSI_RXRSS3R_FMT_Msk                        (0x01000000UL)
#define R_MIPI_DSI_RXRSS3R_FMT_Pos                        (24UL)
#define R_MIPI_DSI_RXRSS3R_RXSUC_Msk                      (0x02000000UL)
#define R_MIPI_DSI_RXRSS3R_RXSUC_Pos                      (25UL)
#define R_MIPI_DSI_RXRSS3R_RXFATALERR_Msk                 (0x04000000UL)
#define R_MIPI_DSI_RXRSS3R_RXFATALERR_Pos                 (26UL)
#define R_MIPI_DSI_RXRSS3R_RXFAIL_Msk                     (0x08000000UL)
#define R_MIPI_DSI_RXRSS3R_RXFAIL_Pos                     (27UL)
#define R_MIPI_DSI_RXRSS3R_RXPKTDFAIL_Msk                 (0x10000000UL)
#define R_MIPI_DSI_RXRSS3R_RXPKTDFAIL_Pos                 (28UL)
#define R_MIPI_DSI_RXRSS3R_RXCORERR_Msk                   (0x20000000UL)
#define R_MIPI_DSI_RXRSS3R_RXCORERR_Pos                   (29UL)
#define R_MIPI_DSI_RXRSS3R_RXAKE_Msk                      (0x40000000UL)
#define R_MIPI_DSI_RXRSS3R_RXAKE_Pos                      (30UL)
#define R_MIPI_DSI_RXRSS3R_INFOOW_Msk                     (0x80000000UL)
#define R_MIPI_DSI_RXRSS3R_INFOOW_Pos                     (31UL)
#define R_MIPI_DSI_RXPPD0R_DATA_Msk                       (0xFFFFFFFFUL)
#define R_MIPI_DSI_RXPPD0R_DATA_Pos                       (0UL)
#define R_MIPI_DSI_RXPPD1R_DATA_Msk                       (0xFFFFFFFFUL)
#define R_MIPI_DSI_RXPPD1R_DATA_Pos                       (0UL)
#define R_MIPI_DSI_RXPPD2R_DATA_Msk                       (0xFFFFFFFFUL)
#define R_MIPI_DSI_RXPPD2R_DATA_Pos                       (0UL)
#define R_MIPI_DSI_RXPPD3R_DATA_Msk                       (0xFFFFFFFFUL)
#define R_MIPI_DSI_RXPPD3R_DATA_Pos                       (0UL)
#define R_MIPI_DSI_HSTXTOSETR_HTXTO_Msk                   (0xFFFFFFFFUL)
#define R_MIPI_DSI_HSTXTOSETR_HTXTO_Pos                   (0UL)
#define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Msk                  (0xFFFFFFFFUL)
#define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Pos                  (0UL)
#define R_MIPI_DSI_TATOSETR_TATO_Msk                      (0xFFFFFFFFUL)
#define R_MIPI_DSI_TATOSETR_TATO_Pos                      (0UL)
#define R_MIPI_DSI_FERRSR_HTXTO_Msk                       (0x00000001UL)
#define R_MIPI_DSI_FERRSR_HTXTO_Pos                       (0UL)
#define R_MIPI_DSI_FERRSR_LRXHTO_Msk                      (0x00000002UL)
#define R_MIPI_DSI_FERRSR_LRXHTO_Pos                      (1UL)
#define R_MIPI_DSI_FERRSR_TATO_Msk                        (0x00000004UL)
#define R_MIPI_DSI_FERRSR_TATO_Pos                        (2UL)
#define R_MIPI_DSI_FERRSR_ERRESC_Msk                      (0x00010000UL)
#define R_MIPI_DSI_FERRSR_ERRESC_Pos                      (16UL)
#define R_MIPI_DSI_FERRSR_ERRSYNESC_Msk                   (0x00020000UL)
#define R_MIPI_DSI_FERRSR_ERRSYNESC_Pos                   (17UL)
#define R_MIPI_DSI_FERRSR_ERRCTRL_Msk                     (0x00040000UL)
#define R_MIPI_DSI_FERRSR_ERRCTRL_Pos                     (18UL)
#define R_MIPI_DSI_FERRSR_ERRCLP0_Msk                     (0x00080000UL)
#define R_MIPI_DSI_FERRSR_ERRCLP0_Pos                     (19UL)
#define R_MIPI_DSI_FERRSR_ERRCLP1_Msk                     (0x00100000UL)
#define R_MIPI_DSI_FERRSR_ERRCLP1_Pos                     (20UL)
#define R_MIPI_DSI_FERRSR_ERRCLP0S_Msk                    (0x08000000UL)
#define R_MIPI_DSI_FERRSR_ERRCLP0S_Pos                    (27UL)
#define R_MIPI_DSI_FERRSR_ERRCLP1S_Msk                    (0x10000000UL)
#define R_MIPI_DSI_FERRSR_ERRCLP1S_Pos                    (28UL)
#define R_MIPI_DSI_FERRSCR_HTXTO_Msk                      (0x00000001UL)
#define R_MIPI_DSI_FERRSCR_HTXTO_Pos                      (0UL)
#define R_MIPI_DSI_FERRSCR_LRXHTO_Msk                     (0x00000002UL)
#define R_MIPI_DSI_FERRSCR_LRXHTO_Pos                     (1UL)
#define R_MIPI_DSI_FERRSCR_TATO_Msk                       (0x00000004UL)
#define R_MIPI_DSI_FERRSCR_TATO_Pos                       (2UL)
#define R_MIPI_DSI_FERRSCR_ERRESC_Msk                     (0x00010000UL)
#define R_MIPI_DSI_FERRSCR_ERRESC_Pos                     (16UL)
#define R_MIPI_DSI_FERRSCR_ERRSYNESC_Msk                  (0x00020000UL)
#define R_MIPI_DSI_FERRSCR_ERRSYNESC_Pos                  (17UL)
#define R_MIPI_DSI_FERRSCR_ERRCTRL_Msk                    (0x00040000UL)
#define R_MIPI_DSI_FERRSCR_ERRCTRL_Pos                    (18UL)
#define R_MIPI_DSI_FERRSCR_ERRCLP0_Msk                    (0x00080000UL)
#define R_MIPI_DSI_FERRSCR_ERRCLP0_Pos                    (19UL)
#define R_MIPI_DSI_FERRSCR_ERRCLP1_Msk                    (0x00100000UL)
#define R_MIPI_DSI_FERRSCR_ERRCLP1_Pos                    (20UL)
#define R_MIPI_DSI_FERRIER_HTXTO_Msk                      (0x00000001UL)
#define R_MIPI_DSI_FERRIER_HTXTO_Pos                      (0UL)
#define R_MIPI_DSI_FERRIER_LRXHTO_Msk                     (0x00000002UL)
#define R_MIPI_DSI_FERRIER_LRXHTO_Pos                     (1UL)
#define R_MIPI_DSI_FERRIER_TATO_Msk                       (0x00000004UL)
#define R_MIPI_DSI_FERRIER_TATO_Pos                       (2UL)
#define R_MIPI_DSI_FERRIER_ERRESC_Msk                     (0x00010000UL)
#define R_MIPI_DSI_FERRIER_ERRESC_Pos                     (16UL)
#define R_MIPI_DSI_FERRIER_ERRSYNESC_Msk                  (0x00020000UL)
#define R_MIPI_DSI_FERRIER_ERRSYNESC_Pos                  (17UL)
#define R_MIPI_DSI_FERRIER_ERRCTRL_Msk                    (0x00040000UL)
#define R_MIPI_DSI_FERRIER_ERRCTRL_Pos                    (18UL)
#define R_MIPI_DSI_FERRIER_ERRCLP0_Msk                    (0x00080000UL)
#define R_MIPI_DSI_FERRIER_ERRCLP0_Pos                    (19UL)
#define R_MIPI_DSI_FERRIER_ERRCLP1_Msk                    (0x00100000UL)
#define R_MIPI_DSI_FERRIER_ERRCLP1_Pos                    (20UL)
#define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Msk                 (0x00000FFCUL)
#define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Pos                 (2UL)
#define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Msk                 (0x00FF0000UL)
#define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Pos                 (16UL)
#define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Msk                  (0xFF000000UL)
#define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Pos                  (24UL)
#define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Msk                (0x000003FFUL)
#define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Pos                (0UL)
#define R_MIPI_DSI_PLSR_CLULPSACTN_Msk                    (0x00000001UL)
#define R_MIPI_DSI_PLSR_CLULPSACTN_Pos                    (0UL)
#define R_MIPI_DSI_PLSR_CLSTPST_Msk                       (0x00000002UL)
#define R_MIPI_DSI_PLSR_CLSTPST_Pos                       (1UL)
#define R_MIPI_DSI_PLSR_DL0RXLPDTESC_Msk                  (0x00000004UL)
#define R_MIPI_DSI_PLSR_DL0RXLPDTESC_Pos                  (2UL)
#define R_MIPI_DSI_PLSR_DL0RXULPSESC_Msk                  (0x00000008UL)
#define R_MIPI_DSI_PLSR_DL0RXULPSESC_Pos                  (3UL)
#define R_MIPI_DSI_PLSR_DLULPSACTN_Msk                    (0x000000F0UL)
#define R_MIPI_DSI_PLSR_DLULPSACTN_Pos                    (4UL)
#define R_MIPI_DSI_PLSR_DLSTPST_Msk                       (0x00000F00UL)
#define R_MIPI_DSI_PLSR_DLSTPST_Pos                       (8UL)
#define R_MIPI_DSI_PLSR_DL0RX2TX_Msk                      (0x00001000UL)
#define R_MIPI_DSI_PLSR_DL0RX2TX_Pos                      (12UL)
#define R_MIPI_DSI_PLSR_DL0TX2RX_Msk                      (0x00002000UL)
#define R_MIPI_DSI_PLSR_DL0TX2RX_Pos                      (13UL)
#define R_MIPI_DSI_PLSR_DL0DIR_Msk                        (0x00008000UL)
#define R_MIPI_DSI_PLSR_DL0DIR_Pos                        (15UL)
#define R_MIPI_DSI_PLSR_CLTOULPS_Msk                      (0x01000000UL)
#define R_MIPI_DSI_PLSR_CLTOULPS_Pos                      (24UL)
#define R_MIPI_DSI_PLSR_CLFROMULPS_Msk                    (0x02000000UL)
#define R_MIPI_DSI_PLSR_CLFROMULPS_Pos                    (25UL)
#define R_MIPI_DSI_PLSR_CLLP2HS_Msk                       (0x04000000UL)
#define R_MIPI_DSI_PLSR_CLLP2HS_Pos                       (26UL)
#define R_MIPI_DSI_PLSR_CLHS2LP_Msk                       (0x08000000UL)
#define R_MIPI_DSI_PLSR_CLHS2LP_Pos                       (27UL)
#define R_MIPI_DSI_PLSR_DLTOULPS_Msk                      (0x10000000UL)
#define R_MIPI_DSI_PLSR_DLTOULPS_Pos                      (28UL)
#define R_MIPI_DSI_PLSR_DLFROMULPS_Msk                    (0x20000000UL)
#define R_MIPI_DSI_PLSR_DLFROMULPS_Pos                    (29UL)
#define R_MIPI_DSI_PLSCR_DL0RX2TX_Msk                     (0x00001000UL)
#define R_MIPI_DSI_PLSCR_DL0RX2TX_Pos                     (12UL)
#define R_MIPI_DSI_PLSCR_DL0TX2RX_Msk                     (0x00002000UL)
#define R_MIPI_DSI_PLSCR_DL0TX2RX_Pos                     (13UL)
#define R_MIPI_DSI_PLSCR_CLTOULPS_Msk                     (0x01000000UL)
#define R_MIPI_DSI_PLSCR_CLTOULPS_Pos                     (24UL)
#define R_MIPI_DSI_PLSCR_CLFROMULPS_Msk                   (0x02000000UL)
#define R_MIPI_DSI_PLSCR_CLFROMULPS_Pos                   (25UL)
#define R_MIPI_DSI_PLSCR_CLLP2HS_Msk                      (0x04000000UL)
#define R_MIPI_DSI_PLSCR_CLLP2HS_Pos                      (26UL)
#define R_MIPI_DSI_PLSCR_CLHS2LP_Msk                      (0x08000000UL)
#define R_MIPI_DSI_PLSCR_CLHS2LP_Pos                      (27UL)
#define R_MIPI_DSI_PLSCR_DLTOULPS_Msk                     (0x10000000UL)
#define R_MIPI_DSI_PLSCR_DLTOULPS_Pos                     (28UL)
#define R_MIPI_DSI_PLSCR_DLFROMULPS_Msk                   (0x20000000UL)
#define R_MIPI_DSI_PLSCR_DLFROMULPS_Pos                   (29UL)
#define R_MIPI_DSI_PLIER_DL0RX2TX_Msk                     (0x00001000UL)
#define R_MIPI_DSI_PLIER_DL0RX2TX_Pos                     (12UL)
#define R_MIPI_DSI_PLIER_DL0TX2RX_Msk                     (0x00002000UL)
#define R_MIPI_DSI_PLIER_DL0TX2RX_Pos                     (13UL)
#define R_MIPI_DSI_PLIER_CLTOULPS_Msk                     (0x01000000UL)
#define R_MIPI_DSI_PLIER_CLTOULPS_Pos                     (24UL)
#define R_MIPI_DSI_PLIER_CLFROMULPS_Msk                   (0x02000000UL)
#define R_MIPI_DSI_PLIER_CLFROMULPS_Pos                   (25UL)
#define R_MIPI_DSI_PLIER_CLLP2HS_Msk                      (0x04000000UL)
#define R_MIPI_DSI_PLIER_CLLP2HS_Pos                      (26UL)
#define R_MIPI_DSI_PLIER_CLHS2LP_Msk                      (0x08000000UL)
#define R_MIPI_DSI_PLIER_CLHS2LP_Pos                      (27UL)
#define R_MIPI_DSI_PLIER_DLTOULPS_Msk                     (0x10000000UL)
#define R_MIPI_DSI_PLIER_DLTOULPS_Pos                     (28UL)
#define R_MIPI_DSI_PLIER_DLFROMULPS_Msk                   (0x20000000UL)
#define R_MIPI_DSI_PLIER_DLFROMULPS_Pos                   (29UL)
#define R_MIPI_DSI_VICH1SET0R_VSTART_Msk                  (0x00000001UL)
#define R_MIPI_DSI_VICH1SET0R_VSTART_Pos                  (0UL)
#define R_MIPI_DSI_VICH1SET0R_VSTPAFT_Msk                 (0x00000002UL)
#define R_MIPI_DSI_VICH1SET0R_VSTPAFT_Pos                 (1UL)
#define R_MIPI_DSI_VICH1SET0R_HSANOLP_Msk                 (0x00000100UL)
#define R_MIPI_DSI_VICH1SET0R_HSANOLP_Pos                 (8UL)
#define R_MIPI_DSI_VICH1SET0R_HBPNOLP_Msk                 (0x00000200UL)
#define R_MIPI_DSI_VICH1SET0R_HBPNOLP_Pos                 (9UL)
#define R_MIPI_DSI_VICH1SET0R_HFPNOLP_Msk                 (0x00000400UL)
#define R_MIPI_DSI_VICH1SET0R_HFPNOLP_Pos                 (10UL)
#define R_MIPI_DSI_VICH1SET0R_VSEN_Msk                    (0x00001000UL)
#define R_MIPI_DSI_VICH1SET0R_VSEN_Pos                    (12UL)
#define R_MIPI_DSI_VICH1SET1R_DLY_Msk                     (0x00003FFCUL)
#define R_MIPI_DSI_VICH1SET1R_DLY_Pos                     (2UL)
#define R_MIPI_DSI_VICH1SET1R_CHBUFSZ_Msk                 (0x00F00000UL)
#define R_MIPI_DSI_VICH1SET1R_CHBUFSZ_Pos                 (20UL)
#define R_MIPI_DSI_VICH1SET1R_BPP_Msk                     (0x3F000000UL)
#define R_MIPI_DSI_VICH1SET1R_BPP_Pos                     (24UL)
#define R_MIPI_DSI_VICH1SET1R_CSPC_Msk                    (0x80000000UL)
#define R_MIPI_DSI_VICH1SET1R_CSPC_Pos                    (31UL)
#define R_MIPI_DSI_VICH1SR_START_Msk                      (0x00000001UL)
#define R_MIPI_DSI_VICH1SR_START_Pos                      (0UL)
#define R_MIPI_DSI_VICH1SR_STOP_Msk                       (0x00000002UL)
#define R_MIPI_DSI_VICH1SR_STOP_Pos                       (1UL)
#define R_MIPI_DSI_VICH1SR_RUNNING_Msk                    (0x00000004UL)
#define R_MIPI_DSI_VICH1SR_RUNNING_Pos                    (2UL)
#define R_MIPI_DSI_VICH1SR_VIRDY_Msk                      (0x00000008UL)
#define R_MIPI_DSI_VICH1SR_VIRDY_Pos                      (3UL)
#define R_MIPI_DSI_VICH1SR_TIMERR_Msk                     (0x00100000UL)
#define R_MIPI_DSI_VICH1SR_TIMERR_Pos                     (20UL)
#define R_MIPI_DSI_VICH1SR_VBUFUDF_Msk                    (0x00400000UL)
#define R_MIPI_DSI_VICH1SR_VBUFUDF_Pos                    (22UL)
#define R_MIPI_DSI_VICH1SR_VBUFOVF_Msk                    (0x00800000UL)
#define R_MIPI_DSI_VICH1SR_VBUFOVF_Pos                    (23UL)
#define R_MIPI_DSI_VICH1SCR_START_Msk                     (0x00000001UL)
#define R_MIPI_DSI_VICH1SCR_START_Pos                     (0UL)
#define R_MIPI_DSI_VICH1SCR_STOP_Msk                      (0x00000002UL)
#define R_MIPI_DSI_VICH1SCR_STOP_Pos                      (1UL)
#define R_MIPI_DSI_VICH1SCR_VIRDY_Msk                     (0x00000008UL)
#define R_MIPI_DSI_VICH1SCR_VIRDY_Pos                     (3UL)
#define R_MIPI_DSI_VICH1SCR_TIMERR_Msk                    (0x00100000UL)
#define R_MIPI_DSI_VICH1SCR_TIMERR_Pos                    (20UL)
#define R_MIPI_DSI_VICH1SCR_VBUFUDF_Msk                   (0x00400000UL)
#define R_MIPI_DSI_VICH1SCR_VBUFUDF_Pos                   (22UL)
#define R_MIPI_DSI_VICH1SCR_VBUFOVF_Msk                   (0x00800000UL)
#define R_MIPI_DSI_VICH1SCR_VBUFOVF_Pos                   (23UL)
#define R_MIPI_DSI_VICH1IER_START_Msk                     (0x00000001UL)
#define R_MIPI_DSI_VICH1IER_START_Pos                     (0UL)
#define R_MIPI_DSI_VICH1IER_STOP_Msk                      (0x00000002UL)
#define R_MIPI_DSI_VICH1IER_STOP_Pos                      (1UL)
#define R_MIPI_DSI_VICH1IER_VIRDY_Msk                     (0x00000008UL)
#define R_MIPI_DSI_VICH1IER_VIRDY_Pos                     (3UL)
#define R_MIPI_DSI_VICH1IER_TIMERR_Msk                    (0x00100000UL)
#define R_MIPI_DSI_VICH1IER_TIMERR_Pos                    (20UL)
#define R_MIPI_DSI_VICH1IER_VBUFUDF_Msk                   (0x00400000UL)
#define R_MIPI_DSI_VICH1IER_VBUFUDF_Pos                   (22UL)
#define R_MIPI_DSI_VICH1IER_VBUFOVF_Msk                   (0x00800000UL)
#define R_MIPI_DSI_VICH1IER_VBUFOVF_Pos                   (23UL)
#define R_MIPI_DSI_VICH1PPSETR_TXESYNC_Msk                (0x00008000UL)
#define R_MIPI_DSI_VICH1PPSETR_TXESYNC_Pos                (15UL)
#define R_MIPI_DSI_VICH1PPSETR_DT_Msk                     (0x003F0000UL)
#define R_MIPI_DSI_VICH1PPSETR_DT_Pos                     (16UL)
#define R_MIPI_DSI_VICH1PPSETR_VC_Msk                     (0x00C00000UL)
#define R_MIPI_DSI_VICH1PPSETR_VC_Pos                     (22UL)
#define R_MIPI_DSI_VICH1VSSETR_VSA_Msk                    (0x00000FFFUL)
#define R_MIPI_DSI_VICH1VSSETR_VSA_Pos                    (0UL)
#define R_MIPI_DSI_VICH1VSSETR_VSPOL_Msk                  (0x00008000UL)
#define R_MIPI_DSI_VICH1VSSETR_VSPOL_Pos                  (15UL)
#define R_MIPI_DSI_VICH1VSSETR_VACTIVE_Msk                (0x7FFF0000UL)
#define R_MIPI_DSI_VICH1VSSETR_VACTIVE_Pos                (16UL)
#define R_MIPI_DSI_VICH1VPSETR_VBP_Msk                    (0x00001FFFUL)
#define R_MIPI_DSI_VICH1VPSETR_VBP_Pos                    (0UL)
#define R_MIPI_DSI_VICH1VPSETR_VFP_Msk                    (0x1FFF0000UL)
#define R_MIPI_DSI_VICH1VPSETR_VFP_Pos                    (16UL)
#define R_MIPI_DSI_VICH1HSSETR_HSA_Msk                    (0x00000FFFUL)
#define R_MIPI_DSI_VICH1HSSETR_HSA_Pos                    (0UL)
#define R_MIPI_DSI_VICH1HSSETR_HSPOL_Msk                  (0x00008000UL)
#define R_MIPI_DSI_VICH1HSSETR_HSPOL_Pos                  (15UL)
#define R_MIPI_DSI_VICH1HSSETR_HACTIVE_Msk                (0x7FFF0000UL)
#define R_MIPI_DSI_VICH1HSSETR_HACTIVE_Pos                (16UL)
#define R_MIPI_DSI_VICH1HPSETR_HBP_Msk                    (0x00001FFFUL)
#define R_MIPI_DSI_VICH1HPSETR_HBP_Pos                    (0UL)
#define R_MIPI_DSI_VICH1HPSETR_HFP_Msk                    (0x1FFF0000UL)
#define R_MIPI_DSI_VICH1HPSETR_HFP_Pos                    (16UL)
#define R_MIPI_DSI_SQCH0SET0R_START_Msk                   (0x00000001UL)
#define R_MIPI_DSI_SQCH0SET0R_START_Pos                   (0UL)
#define R_MIPI_DSI_SQCH0SET1R_CHBUFSZ_Msk                 (0x00F00000UL)
#define R_MIPI_DSI_SQCH0SET1R_CHBUFSZ_Pos                 (20UL)
#define R_MIPI_DSI_SQCH0SET1R_MAXDESNUM_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH0SET1R_MAXDESNUM_Pos               (24UL)
#define R_MIPI_DSI_SQCH0SR_RUNNING_Msk                    (0x00000004UL)
#define R_MIPI_DSI_SQCH0SR_RUNNING_Pos                    (2UL)
#define R_MIPI_DSI_SQCH0SR_AACTFIN_Msk                    (0x00000010UL)
#define R_MIPI_DSI_SQCH0SR_AACTFIN_Pos                    (4UL)
#define R_MIPI_DSI_SQCH0SR_ADESFIN_Msk                    (0x00000100UL)
#define R_MIPI_DSI_SQCH0SR_ADESFIN_Pos                    (8UL)
#define R_MIPI_DSI_SQCH0SR_PKTBIGERR_Msk                  (0x00080000UL)
#define R_MIPI_DSI_SQCH0SR_PKTBIGERR_Pos                  (19UL)
#define R_MIPI_DSI_SQCH0SR_TXIBERR_Msk                    (0x01000000UL)
#define R_MIPI_DSI_SQCH0SR_TXIBERR_Pos                    (24UL)
#define R_MIPI_DSI_SQCH0SR_RXFATALERR_Msk                 (0x04000000UL)
#define R_MIPI_DSI_SQCH0SR_RXFATALERR_Pos                 (26UL)
#define R_MIPI_DSI_SQCH0SR_RXFAIL_Msk                     (0x08000000UL)
#define R_MIPI_DSI_SQCH0SR_RXFAIL_Pos                     (27UL)
#define R_MIPI_DSI_SQCH0SR_RXPKTDFAIL_Msk                 (0x10000000UL)
#define R_MIPI_DSI_SQCH0SR_RXPKTDFAIL_Pos                 (28UL)
#define R_MIPI_DSI_SQCH0SR_RXCORERR_Msk                   (0x20000000UL)
#define R_MIPI_DSI_SQCH0SR_RXCORERR_Pos                   (29UL)
#define R_MIPI_DSI_SQCH0SR_RXAKE_Msk                      (0x40000000UL)
#define R_MIPI_DSI_SQCH0SR_RXAKE_Pos                      (30UL)
#define R_MIPI_DSI_SQCH0SCR_AACTFIN_Msk                   (0x00000010UL)
#define R_MIPI_DSI_SQCH0SCR_AACTFIN_Pos                   (4UL)
#define R_MIPI_DSI_SQCH0SCR_ADESFIN_Msk                   (0x00000100UL)
#define R_MIPI_DSI_SQCH0SCR_ADESFIN_Pos                   (8UL)
#define R_MIPI_DSI_SQCH0SCR_PKTBIGERR_Msk                 (0x00080000UL)
#define R_MIPI_DSI_SQCH0SCR_PKTBIGERR_Pos                 (19UL)
#define R_MIPI_DSI_SQCH0SCR_TXIBERR_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0SCR_TXIBERR_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0SCR_RXFATALERR_Msk                (0x04000000UL)
#define R_MIPI_DSI_SQCH0SCR_RXFATALERR_Pos                (26UL)
#define R_MIPI_DSI_SQCH0SCR_RXFAIL_Msk                    (0x08000000UL)
#define R_MIPI_DSI_SQCH0SCR_RXFAIL_Pos                    (27UL)
#define R_MIPI_DSI_SQCH0SCR_RXPKTDFAIL_Msk                (0x10000000UL)
#define R_MIPI_DSI_SQCH0SCR_RXPKTDFAIL_Pos                (28UL)
#define R_MIPI_DSI_SQCH0SCR_RXCORERR_Msk                  (0x20000000UL)
#define R_MIPI_DSI_SQCH0SCR_RXCORERR_Pos                  (29UL)
#define R_MIPI_DSI_SQCH0SCR_RXAKE_Msk                     (0x40000000UL)
#define R_MIPI_DSI_SQCH0SCR_RXAKE_Pos                     (30UL)
#define R_MIPI_DSI_SQCH0IER_AACTFIN_Msk                   (0x00000010UL)
#define R_MIPI_DSI_SQCH0IER_AACTFIN_Pos                   (4UL)
#define R_MIPI_DSI_SQCH0IER_ADESFIN_Msk                   (0x00000100UL)
#define R_MIPI_DSI_SQCH0IER_ADESFIN_Pos                   (8UL)
#define R_MIPI_DSI_SQCH0IER_PKTBIGERR_Msk                 (0x00080000UL)
#define R_MIPI_DSI_SQCH0IER_PKTBIGERR_Pos                 (19UL)
#define R_MIPI_DSI_SQCH0IER_TXIBERR_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0IER_TXIBERR_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0IER_RXFATALERR_Msk                (0x04000000UL)
#define R_MIPI_DSI_SQCH0IER_RXFATALERR_Pos                (26UL)
#define R_MIPI_DSI_SQCH0IER_RXFAIL_Msk                    (0x08000000UL)
#define R_MIPI_DSI_SQCH0IER_RXFAIL_Pos                    (27UL)
#define R_MIPI_DSI_SQCH0IER_RXPKTDFAIL_Msk                (0x10000000UL)
#define R_MIPI_DSI_SQCH0IER_RXPKTDFAIL_Pos                (28UL)
#define R_MIPI_DSI_SQCH0IER_RXCORERR_Msk                  (0x20000000UL)
#define R_MIPI_DSI_SQCH0IER_RXCORERR_Pos                  (29UL)
#define R_MIPI_DSI_SQCH0IER_RXAKE_Msk                     (0x40000000UL)
#define R_MIPI_DSI_SQCH0IER_RXAKE_Pos                     (30UL)
#define R_MIPI_DSI_SQCH1SET0R_START_Msk                   (0x00000001UL)
#define R_MIPI_DSI_SQCH1SET0R_START_Pos                   (0UL)
#define R_MIPI_DSI_SQCH1SET1R_CHBUFSZ_Msk                 (0x00F00000UL)
#define R_MIPI_DSI_SQCH1SET1R_CHBUFSZ_Pos                 (20UL)
#define R_MIPI_DSI_SQCH1SET1R_MAXDESNUM_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH1SET1R_MAXDESNUM_Pos               (24UL)
#define R_MIPI_DSI_SQCH1SR_RUNNING_Msk                    (0x00000004UL)
#define R_MIPI_DSI_SQCH1SR_RUNNING_Pos                    (2UL)
#define R_MIPI_DSI_SQCH1SR_AACTFIN_Msk                    (0x00000010UL)
#define R_MIPI_DSI_SQCH1SR_AACTFIN_Pos                    (4UL)
#define R_MIPI_DSI_SQCH1SR_ADESFIN_Msk                    (0x00000100UL)
#define R_MIPI_DSI_SQCH1SR_ADESFIN_Pos                    (8UL)
#define R_MIPI_DSI_SQCH1SR_PKTBIGERR_Msk                  (0x00080000UL)
#define R_MIPI_DSI_SQCH1SR_PKTBIGERR_Pos                  (19UL)
#define R_MIPI_DSI_SQCH1SR_TXIBERR_Msk                    (0x01000000UL)
#define R_MIPI_DSI_SQCH1SR_TXIBERR_Pos                    (24UL)
#define R_MIPI_DSI_SQCH1SR_RXFATALERR_Msk                 (0x04000000UL)
#define R_MIPI_DSI_SQCH1SR_RXFATALERR_Pos                 (26UL)
#define R_MIPI_DSI_SQCH1SR_RXFAIL_Msk                     (0x08000000UL)
#define R_MIPI_DSI_SQCH1SR_RXFAIL_Pos                     (27UL)
#define R_MIPI_DSI_SQCH1SR_RXPKTDFAIL_Msk                 (0x10000000UL)
#define R_MIPI_DSI_SQCH1SR_RXPKTDFAIL_Pos                 (28UL)
#define R_MIPI_DSI_SQCH1SR_RXCORERR_Msk                   (0x20000000UL)
#define R_MIPI_DSI_SQCH1SR_RXCORERR_Pos                   (29UL)
#define R_MIPI_DSI_SQCH1SR_RXAKE_Msk                      (0x40000000UL)
#define R_MIPI_DSI_SQCH1SR_RXAKE_Pos                      (30UL)
#define R_MIPI_DSI_SQCH1SCR_AACTFIN_Msk                   (0x00000010UL)
#define R_MIPI_DSI_SQCH1SCR_AACTFIN_Pos                   (4UL)
#define R_MIPI_DSI_SQCH1SCR_ADESFIN_Msk                   (0x00000100UL)
#define R_MIPI_DSI_SQCH1SCR_ADESFIN_Pos                   (8UL)
#define R_MIPI_DSI_SQCH1SCR_PKTBIGERR_Msk                 (0x00080000UL)
#define R_MIPI_DSI_SQCH1SCR_PKTBIGERR_Pos                 (19UL)
#define R_MIPI_DSI_SQCH1SCR_TXIBERR_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1SCR_TXIBERR_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1SCR_RXFATALERR_Msk                (0x04000000UL)
#define R_MIPI_DSI_SQCH1SCR_RXFATALERR_Pos                (26UL)
#define R_MIPI_DSI_SQCH1SCR_RXFAIL_Msk                    (0x08000000UL)
#define R_MIPI_DSI_SQCH1SCR_RXFAIL_Pos                    (27UL)
#define R_MIPI_DSI_SQCH1SCR_RXPKTDFAIL_Msk                (0x10000000UL)
#define R_MIPI_DSI_SQCH1SCR_RXPKTDFAIL_Pos                (28UL)
#define R_MIPI_DSI_SQCH1SCR_RXCORERR_Msk                  (0x20000000UL)
#define R_MIPI_DSI_SQCH1SCR_RXCORERR_Pos                  (29UL)
#define R_MIPI_DSI_SQCH1SCR_RXAKE_Msk                     (0x40000000UL)
#define R_MIPI_DSI_SQCH1SCR_RXAKE_Pos                     (30UL)
#define R_MIPI_DSI_SQCH1IER_AACTFIN_Msk                   (0x00000010UL)
#define R_MIPI_DSI_SQCH1IER_AACTFIN_Pos                   (4UL)
#define R_MIPI_DSI_SQCH1IER_ADESFIN_Msk                   (0x00000100UL)
#define R_MIPI_DSI_SQCH1IER_ADESFIN_Pos                   (8UL)
#define R_MIPI_DSI_SQCH1IER_PKTBIGERR_Msk                 (0x00080000UL)
#define R_MIPI_DSI_SQCH1IER_PKTBIGERR_Pos                 (19UL)
#define R_MIPI_DSI_SQCH1IER_TXIBERR_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1IER_TXIBERR_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1IER_RXFATALERR_Msk                (0x04000000UL)
#define R_MIPI_DSI_SQCH1IER_RXFATALERR_Pos                (26UL)
#define R_MIPI_DSI_SQCH1IER_RXFAIL_Msk                    (0x08000000UL)
#define R_MIPI_DSI_SQCH1IER_RXFAIL_Pos                    (27UL)
#define R_MIPI_DSI_SQCH1IER_RXPKTDFAIL_Msk                (0x10000000UL)
#define R_MIPI_DSI_SQCH1IER_RXPKTDFAIL_Pos                (28UL)
#define R_MIPI_DSI_SQCH1IER_RXCORERR_Msk                  (0x20000000UL)
#define R_MIPI_DSI_SQCH1IER_RXCORERR_Pos                  (29UL)
#define R_MIPI_DSI_SQCH1IER_RXAKE_Msk                     (0x40000000UL)
#define R_MIPI_DSI_SQCH1IER_RXAKE_Pos                     (30UL)
#define R_MIPI_DSI_SQCH0DSC00AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH0DSC00AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC00AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH0DSC00AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH0DSC00AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH0DSC00AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH0DSC00AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH0DSC00AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH0DSC00AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0DSC00AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0DSC00AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH0DSC00AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH0DSC00AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH0DSC00AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH0DSC00AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH0DSC00AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH0DSC00BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH0DSC00BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH0DSC00CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH0DSC00CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH0DSC00CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH0DSC00CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH0DSC00CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH0DSC00CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH0DSC00DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH0DSC00DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC01AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH0DSC01AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC01AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH0DSC01AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH0DSC01AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH0DSC01AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH0DSC01AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH0DSC01AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH0DSC01AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0DSC01AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0DSC01AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH0DSC01AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH0DSC01AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH0DSC01AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH0DSC01AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH0DSC01AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH0DSC01BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH0DSC01BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH0DSC01CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH0DSC01CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH0DSC01CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH0DSC01CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH0DSC01CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH0DSC01CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH0DSC01DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH0DSC01DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC02AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH0DSC02AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC02AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH0DSC02AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH0DSC02AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH0DSC02AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH0DSC02AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH0DSC02AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH0DSC02AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0DSC02AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0DSC02AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH0DSC02AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH0DSC02AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH0DSC02AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH0DSC02AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH0DSC02AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH0DSC02BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH0DSC02BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH0DSC02CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH0DSC02CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH0DSC02CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH0DSC02CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH0DSC02CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH0DSC02CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH0DSC02DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH0DSC02DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC03AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH0DSC03AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC03AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH0DSC03AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH0DSC03AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH0DSC03AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH0DSC03AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH0DSC03AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH0DSC03AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0DSC03AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0DSC03AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH0DSC03AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH0DSC03AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH0DSC03AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH0DSC03AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH0DSC03AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH0DSC03BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH0DSC03BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH0DSC03CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH0DSC03CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH0DSC03CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH0DSC03CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH0DSC03CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH0DSC03CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH0DSC03DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH0DSC03DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC04AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH0DSC04AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC04AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH0DSC04AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH0DSC04AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH0DSC04AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH0DSC04AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH0DSC04AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH0DSC04AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0DSC04AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0DSC04AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH0DSC04AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH0DSC04AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH0DSC04AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH0DSC04AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH0DSC04AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH0DSC04BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH0DSC04BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH0DSC04CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH0DSC04CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH0DSC04CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH0DSC04CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH0DSC04CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH0DSC04CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH0DSC04DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH0DSC04DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC05AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH0DSC05AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC05AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH0DSC05AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH0DSC05AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH0DSC05AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH0DSC05AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH0DSC05AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH0DSC05AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0DSC05AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0DSC05AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH0DSC05AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH0DSC05AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH0DSC05AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH0DSC05AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH0DSC05AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH0DSC05BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH0DSC05BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH0DSC05CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH0DSC05CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH0DSC05CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH0DSC05CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH0DSC05CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH0DSC05CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH0DSC05DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH0DSC05DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC06AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH0DSC06AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC06AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH0DSC06AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH0DSC06AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH0DSC06AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH0DSC06AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH0DSC06AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH0DSC06AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0DSC06AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0DSC06AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH0DSC06AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH0DSC06AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH0DSC06AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH0DSC06AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH0DSC06AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH0DSC06BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH0DSC06BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH0DSC06CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH0DSC06CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH0DSC06CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH0DSC06CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH0DSC06CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH0DSC06CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH0DSC06DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH0DSC06DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC07AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH0DSC07AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH0DSC07AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH0DSC07AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH0DSC07AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH0DSC07AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH0DSC07AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH0DSC07AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH0DSC07AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH0DSC07AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH0DSC07AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH0DSC07AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH0DSC07AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH0DSC07AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH0DSC07AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH0DSC07AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH0DSC07BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH0DSC07BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH0DSC07CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH0DSC07CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH0DSC07CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH0DSC07CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH0DSC07CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH0DSC07CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH0DSC07DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH0DSC07DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC00AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH1DSC00AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC00AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH1DSC00AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH1DSC00AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH1DSC00AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH1DSC00AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH1DSC00AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH1DSC00AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1DSC00AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1DSC00AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH1DSC00AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH1DSC00AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH1DSC00AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH1DSC00AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH1DSC00AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH1DSC00BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH1DSC00BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH1DSC00CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH1DSC00CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH1DSC00CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH1DSC00CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH1DSC00CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH1DSC00CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH1DSC00DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH1DSC00DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC01AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH1DSC01AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC01AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH1DSC01AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH1DSC01AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH1DSC01AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH1DSC01AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH1DSC01AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH1DSC01AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1DSC01AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1DSC01AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH1DSC01AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH1DSC01AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH1DSC01AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH1DSC01AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH1DSC01AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH1DSC01BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH1DSC01BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH1DSC01CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH1DSC01CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH1DSC01CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH1DSC01CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH1DSC01CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH1DSC01CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH1DSC01DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH1DSC01DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC02AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH1DSC02AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC02AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH1DSC02AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH1DSC02AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH1DSC02AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH1DSC02AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH1DSC02AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH1DSC02AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1DSC02AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1DSC02AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH1DSC02AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH1DSC02AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH1DSC02AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH1DSC02AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH1DSC02AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH1DSC02BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH1DSC02BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH1DSC02CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH1DSC02CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH1DSC02CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH1DSC02CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH1DSC02CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH1DSC02CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH1DSC02DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH1DSC02DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC03AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH1DSC03AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC03AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH1DSC03AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH1DSC03AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH1DSC03AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH1DSC03AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH1DSC03AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH1DSC03AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1DSC03AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1DSC03AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH1DSC03AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH1DSC03AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH1DSC03AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH1DSC03AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH1DSC03AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH1DSC03BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH1DSC03BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH1DSC03CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH1DSC03CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH1DSC03CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH1DSC03CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH1DSC03CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH1DSC03CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH1DSC03DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH1DSC03DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC04AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH1DSC04AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC04AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH1DSC04AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH1DSC04AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH1DSC04AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH1DSC04AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH1DSC04AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH1DSC04AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1DSC04AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1DSC04AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH1DSC04AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH1DSC04AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH1DSC04AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH1DSC04AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH1DSC04AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH1DSC04BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH1DSC04BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH1DSC04CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH1DSC04CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH1DSC04CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH1DSC04CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH1DSC04CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH1DSC04CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH1DSC04DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH1DSC04DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC05AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH1DSC05AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC05AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH1DSC05AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH1DSC05AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH1DSC05AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH1DSC05AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH1DSC05AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH1DSC05AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1DSC05AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1DSC05AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH1DSC05AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH1DSC05AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH1DSC05AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH1DSC05AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH1DSC05AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH1DSC05BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH1DSC05BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH1DSC05CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH1DSC05CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH1DSC05CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH1DSC05CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH1DSC05CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH1DSC05CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH1DSC05DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH1DSC05DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC06AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH1DSC06AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC06AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH1DSC06AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH1DSC06AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH1DSC06AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH1DSC06AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH1DSC06AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH1DSC06AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1DSC06AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1DSC06AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH1DSC06AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH1DSC06AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH1DSC06AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH1DSC06AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH1DSC06AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH1DSC06BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH1DSC06BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH1DSC06CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH1DSC06CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH1DSC06CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH1DSC06CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH1DSC06CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH1DSC06CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH1DSC06DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH1DSC06DR_LADDR_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC07AR_DATA0_Msk                 (0x000000FFUL)
#define R_MIPI_DSI_SQCH1DSC07AR_DATA0_Pos                 (0UL)
#define R_MIPI_DSI_SQCH1DSC07AR_DATA1_Msk                 (0x0000FF00UL)
#define R_MIPI_DSI_SQCH1DSC07AR_DATA1_Pos                 (8UL)
#define R_MIPI_DSI_SQCH1DSC07AR_DT_Msk                    (0x003F0000UL)
#define R_MIPI_DSI_SQCH1DSC07AR_DT_Pos                    (16UL)
#define R_MIPI_DSI_SQCH1DSC07AR_VC_Msk                    (0x00C00000UL)
#define R_MIPI_DSI_SQCH1DSC07AR_VC_Pos                    (22UL)
#define R_MIPI_DSI_SQCH1DSC07AR_FMT_Msk                   (0x01000000UL)
#define R_MIPI_DSI_SQCH1DSC07AR_FMT_Pos                   (24UL)
#define R_MIPI_DSI_SQCH1DSC07AR_SPD_Msk                   (0x02000000UL)
#define R_MIPI_DSI_SQCH1DSC07AR_SPD_Pos                   (25UL)
#define R_MIPI_DSI_SQCH1DSC07AR_BTA_Msk                   (0x0C000000UL)
#define R_MIPI_DSI_SQCH1DSC07AR_BTA_Pos                   (26UL)
#define R_MIPI_DSI_SQCH1DSC07AR_NXACT_Msk                 (0x30000000UL)
#define R_MIPI_DSI_SQCH1DSC07AR_NXACT_Pos                 (28UL)
#define R_MIPI_DSI_SQCH1DSC07BR_DTSEL_Msk                 (0x03000000UL)
#define R_MIPI_DSI_SQCH1DSC07BR_DTSEL_Pos                 (24UL)
#define R_MIPI_DSI_SQCH1DSC07CR_FINACT_Msk                (0x00000007UL)
#define R_MIPI_DSI_SQCH1DSC07CR_FINACT_Pos                (0UL)
#define R_MIPI_DSI_SQCH1DSC07CR_AUXOP_Msk                 (0x00400000UL)
#define R_MIPI_DSI_SQCH1DSC07CR_AUXOP_Pos                 (22UL)
#define R_MIPI_DSI_SQCH1DSC07CR_ACTCODE_Msk               (0xFF000000UL)
#define R_MIPI_DSI_SQCH1DSC07CR_ACTCODE_Pos               (24UL)
#define R_MIPI_DSI_SQCH1DSC07DR_LADDR_Msk                 (0xFFFFFFFFUL)
#define R_MIPI_DSI_SQCH1DSC07DR_LADDR_Pos                 (0UL)

#endif
